SI & PI Simulation

Accelerate Time to Signal and Power Integrity Compliance

SI & PI Simulation

Will Sparrow SI & PI Simulation Services Signal integrity is fundamental to any modern electronic system. The industry uses the term “integrity” as it means adhering to a code, remaining unimpaired, and being complete and undivided. If the waveform of the signal varies significantly from the original because of crosstalk, impedance mismatch, and losses, the receiver will not be able to read the signal, creating a signal integrity issue. That is why signal integrity engineering — analyzing and improving signal integrity issues — is an important part of designing integrated circuits (ICs), IC packages, and printed circuit boards (PCBs).

A system's signal integrity (SI) is a measure of how much an electrical signal changes between entering and exiting a circuit. For digital electronics, that signal is an electric current in which voltage varies between a high and a low value over time.

Engineering Team
High-speed PCB layout design

Signal Integrity

Delivering precise solutions for the most demanding high-speed designs

Core Capabilities

Advanced expertise in high-speed electronic design and signal integrity:

High-Speed Layout Design

DDR3/4, SAS, PCIe3/4, Flash, Ethernet PHY, and Backplane interfaces

Channel Modeling

Optimization techniques for 28Gbps+ signal performance

DC IR Drop

Decoupling capacitor optimization for power integrity

3D EM Modeling

Complex structures: PCB via, IC package & Connectors

SI Analysis

Proficient in signal integrity analysis reports

Prototype Validation

Using high-speed scopes and TDR equipment

Discuss Your Project

Intelligent Design Flow

Our revolutionary methodology ensures optimal signal and power integrity through every stage of your design journey

01
PCB Stackup Design

Stackup Design

Impedance Control High-Speed
  • Advanced material selection (Core, Prepreg, and copper foil)
  • Sophisticated via constructions – Thru, Blind/Buried, Backdrill
  • Precision characteristic impedance (Zo) control – SE, DP

Pre-layout Analysis

  • Advanced termination strategies & comprehensive loss and crosstalk modeling
  • Intelligent ODT and drive strength optimization for signal integrity
  • Cutting-edge channel modeling and simulation up to 112Gbps and beyond
  • Detailed layout guidelines with rule verification methodology
02
Pre-layout Analysis

Pre-layout Analysis

Signal Integrity Simulation
  • Advanced termination strategies & loss and crosstalk modeling
  • Intelligent ODT and drive strength optimization
  • Channel modeling up to 112Gbps and beyond
03
Post-layout Analysis

Post-layout Analysis

Power Integrity Verification
  • DC IR Drop analysis with advanced power plane optimization
  • Decoupling capacitor placement and value optimization
  • Full-spectrum crosstalk analysis with hotspot detection
ADVANCED STAGE

Design Verification

Our comprehensive verification methodology ensures your design meets all performance requirements before manufacturing

Design Rule Checks

Automated verification against manufacturability constraints

Signal Integrity

Advanced waveform analysis and margin assessment

Power Integrity

PDN impedance and transient response verification

EMI/EMC Analysis

Pre-compliance assessment and optimization

Design Verification
Verification Report
PASSING

DCIR Drop analysis

Goal: Enhance DDR4 clock speed for better performance

DCIR Drop Analysis Visualization

Problem Statement:

Increase in Current density(mA/mil2) at neckdown region, which cause power loss and heating on board

Recommendation:

Increase the shape (Plane) width at the high current density region.

DDR4 Clock optimization

Goal: Evaluate voltage drop across a power delivery network (PDN) in a PCB

DCIR Drop Analysis Visualization

Problem Statement:

Reflection on DDR4_CLKN/P reduces the eye diagram margin, as CLK termination was present at FPGA side

Recommendation:

Move the CLK termination scheme from Controller(FPGA) to Memory(DDR4) side

PDN AC - De-Cap optimization

Goal: Ensure stable power to all chips in system with increasing PCB complexity and decreasing system size. Optimizing decaps locations and values in design phase will reduce risk of board re-spin. Stability of power rail to critical chips can be ensured by keeping the impedance of power rail below a specific target.

DCIR Drop Analysis Visualization

Via optimization for 56Gbps data rate

Goal: In high-speed designs, any small discontinuity in physical geometries along transmission path can degrade signal. This degradation includes loss of signal amplitude, change of signal rise time and increased jitter etc. PCB vias are a source of impedance discontinuities if not properly designed. The via stub, antipad size, drill hole size, and differential via pitch are important features for via impedance control.

DCIR Drop Analysis Visualization

FEXT Optimization

DCIR Drop Analysis Visualization

Correlation - Simulation Vs Test

DCIR Drop Analysis Visualization
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